Technical Field
The present disclosure relates to a continuous-time comparator circuit of a high-speed type.
Description of the Related Art
As is known, today available are electronic circuits known as comparators, which are designed to compare an input signal, typically a voltage signal, with a reference signal, typically represented by a reference voltage, and to generate an output signal, which indicates the fact that the input signal is higher or lower than the reference signal.
In detail, comparators of the so-called clock-triggered type are known, in which the so-called decision of the comparator, i.e., switching of the output signal between a first value and a second value following upon crossing, by the input signal, of the voltage level represented by the reference voltage, takes place synchronously with a timing signal of a periodic type, generally known as clock signal. In particular, the decisions are made on the edges of the clock signal; typically, the decisions are made at the rising edges of the clock signal, whereas at the falling edges a reset is made.
In general, clock-triggered comparators make the respective decisions in very short times, since they implement latch mechanisms, which are characterized by a positive feedback. Consequently, clock-triggered comparators are characterized by a high speed and a high resolution; i.e., they are able to switch their own output signals following upon minimal deviations between the input signals and the reference voltages. However, clock-triggered comparators must in fact implement a circuitry of the reset latch type and further may not be used in the cases where it is necessary to monitor the input signal continuously.
In order to provide comparators capable of overcoming at least in part the drawbacks associated with clock-triggered comparators, comparators of a signal-triggered type have been proposed, which are also known as “continuous-time comparators”, where the decision is taken at the moment when the input signal crosses a signal level equal to the level of the reference signal. In this case, the clock signal is not used, and the comparator continuously monitors the input signal.
In greater detail, FIG. 1 shows a continuous-time comparator circuit 1.
The comparator circuit 1 comprises a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, and an eighth MOSFET M8, which operate in saturation regime. The comparator circuit 1 further comprises a current generator 2 designed to generate a current IB0 of a d.c. type.
In detail, the first and second MOSFETs M1, M2 form a differential pair and are of the P-channel-enrichment type. In particular, the source terminals of the first and second MOSFETs M1, M2 are connected to a first terminal of the current generator 2, the second terminal of which is connected to a first node N1, which in use is set at a supply voltage Vcc, for example, 3 V.
The gate terminals of the first and second MOSFETs M1, M2 form, respectively, a negative input terminal and a positive input terminal of the comparator circuit 1, which are designed to receive, respectively, the input signal and the reference signal (or vice versa), the latter signal being formed, for example, by a reference voltage.
The drain terminals of the first and second MOSFETs M1, M2 are connected, respectively, to the drain terminals of the third and fourth MOSFETs M3, M4, which are MOSFETs of the N-channel-enrichment type. More in particular, each one of the third and fourth MOSFETs M3, M4 is diode-connected. Consequently, the gate terminals of the third and fourth MOSFETs M3, M4 are connected, respectively, to the drain terminals of the third and fourth MOSFETs M3,M4; the gate terminals of the third and fourth MOSFETs M3, M4 are thus connected, respectively, to the drain terminals of the first and second MOSFETs M1, M2.
The source terminals of the third and fourth MOSFETs M3, M4 are connected to a second node N2, which, in use, may be set at ground.
The fifth and sixth MOSFETs M5, M6 are of the N-channel-enrichment type. Further, the gate terminal and the source terminal of the fifth MOSFET M5 are connected, respectively, to the gate terminal of the third MOSFET M3 and to the second node N2. The gate terminal and the source terminal of the sixth MOSFET M6 are connected, respectively, to the gate terminal of the fourth MOSFET M4 and to the second node N2.
The seventh and eighth MOSFETs M7, M8 are of the P-channel-enrichment type.
The source terminals of the seventh and eighth MOSFETs M7, M8 are connected to the first node N1. The gate terminals of the seventh and eighth MOSFETs M7, M8 are connected together.
The drain terminals of the seventh and eighth MOSFETs M7, M8 are connected, respectively, to the drain terminals of the fifth and sixth MOSFETs M5, M6. Further, the seventh MOSFET M7 is diode-connected; consequently, the drain terminal and the gate terminal of the seventh MOSFET M7 are connected together.
In greater detail, the first and second MOSFETs M1, M2 are the same as one another. The seventh and eighth MOSFETs M7, M8 are the same as one another. Further, the third and fourth MOSFETs M3, M4 are the same as one another; in addition, the fifth and sixth MOSFETs M5, M6 are the same as one another; these MOSFETs are such that the following relations apply: (W/L)M5=(W/L)M6=k·(W/L)M3=k·(W/L)M4, where (W/L)M5, (W/L)M6, (W/L)M3 and (W/L)M4 represent, respectively, the so-called W/L ratios for the channels of the fifth, sixth, third, and fourth MOSFETs M5, M6, M3, M4.
In practice, as mentioned previously, the first and second MOSFETs M1, M2 form the input transistors of a differential pair, the load transistors of which are formed by the third and fourth MOSFETs M3, M4. Further, the drain terminals of the sixth and eighth MOSFETs M6, M8 form a third node N3, which represents an output node.
The comparator circuit 1 further comprises a cascade of inverters 6, which are connected in series, the input of the first inverter being connected to the third node N3.
In practice, if IB1 and IB2 are, respectively, the currents that flow in the first and second MOSFETs M1, M2, respectively, the following relations apply:IB1=(IB0/2)+ΔIB2=(IB0/2)−Δwhere the Δ sign depends upon the relation between the input signal and the reference voltage. For instance, if the reference voltage, present on the gate terminal of the second MOSFET M2, is higher than the input signal, present on the gate terminal of the first MOSFET M1, Δ is positive; instead, if the reference voltage is lower than the input signal, Δ is negative.
The third and fifth MOSFETs M3, M5 form a first current mirror, so that flowing in the fifth MOSFET M5 is a current I* equal to the current IB1. Likewise, the fourth and sixth MOSFETs M4, M6 form a second current mirror, so that flowing in the sixth MOSFET M6 is a current I** equal to the current IB2.
The seventh and eighth MOSFETs M7, M8 form a third current mirror, so that flowing in the eighth MOSFET M8 is a current I*** equal to the current I*, and thus to the current IB1.
Operatively, the comparator circuit 1 functions as described in what follows, assuming that, following upon an instant (known as “crossing time”) at which the input signal and the reference voltage assume one and the same value, the input signal assumes a value that differs from the value assumed at the crossing time and is such thatIB1=(IB0/2)+ΔIB2=(IB0/2)−Δwith Δ positive; at the crossing time, Δ=0. In practice, it is assumed that the input signal crosses the value of the reference voltage in its descending stretch.
This having been said, on account of the presence of the first, second, and third current mirrors, we have:I***=IB1=(IB0/2)+ΔIB2=(IB0/2)−ΔI**=IB2=(IB0/2)−Δ
Further, the voltage present on the drain terminal of the third MOSFET M3 increases with respect to the corresponding value assumed at the crossing time, whereas the voltage present on the drain terminal of the fourth MOSFET M4 decreases with respect to the corresponding value assumed at the crossing time. In this connection, the impedance seen by the drain terminal of the first MOSFET M1 towards the second node N2 is equal to 1/gm, where gm is the transconductance of the third MOSFET M3. Also the impedance seen by the drain terminal of the second MOSFET M2 towards the second node N2 is equal to 1/gm since it is assumed that the third and fourth MOSFETs M3, M4 are the same.
In addition, since in the eighth MOSFET M8 there flows more current than in the sixth MOSFET M6, the voltage on the third node N3 tends to increase, going to a high value.
In the case where Δ were negative, i.e., in the case where the input signal were to cross the value of the reference voltage in the ascending stretch, the behavior of the comparator circuit 1 would be opposite to what has been described.
Switching of the voltage present on the third node N3 from the low value to the value high (or vice versa) causes in succession switching of the outputs of the inverters 6 and thus represents a sort of preliminary output signal. Present on the output of the last inverter 6 is a voltage VOUT, which forms the output signal of the comparator circuit 1. Switching of the voltage VOUT, as also switching of the preliminary output signal, indicates crossing, by the input signal, of the voltage value indicated by the reference voltage, in addition to indicating the relation between the input signal and the reference voltage.
Irrespective of the presence of the inverters 6, the comparator circuit 1 is characterized in that it implements a sort of negative feedback. In fact, observing, for example, the first and third MOSFETs M1, M3, it may be noted how, if the voltage present on the drain terminal of the third MOSFET M3 tends to increase on account of an increase in the current IB1, also the voltage present on the gate terminal of the third MOSFET M3 tends to increase. Since an increase in the voltage present on the gate terminal of the third MOSFET M3 induces a reduction of the voltage present on the drain terminal of the third MOSFET M3, the latter voltage is subject to a negative-feedback mechanism, as is also true for the voltage present on the drain terminal of the fourth MOSFET M4. The comparator circuit 1 does not thus require any reset, but is characterized by relatively long times for switching of the voltage on the third node N3. Further, the comparator circuit 1 has a relatively low gain; i.e., following upon the crossing time, it is necessary for the voltage of the input signal to differ from the reference voltage by a non-negligible deviation, for the comparator circuit 1 to carry out switching.
In order to speed up the response of the comparator, and in particular in order to speed up the variations of voltage on the third node N3, the comparator circuit 10 illustrated in FIG. 2 has been proposed, which is described in what follows limitedly to the differences with respect to the comparator circuit 1. Further, components of the comparator circuit 10 already present in the comparator circuit 1 are designated by the same references.
In detail, the comparator circuit 10 comprises a ninth MOSFET M3X and a tenth MOSFET M4X, referred to in what follows as the first feedback MOSFET M3X and the second feedback MOSFET M4X, respectively.
The first and second feedback MOSFETs M3X, M4X are of the N-channel-enrichment type and are the same as one another.
The drain and source terminals of the first feedback MOSFET M3X are connected, respectively, to the drain terminal of the third MOSFET M3 and to the second node N2. The gate terminal of the first feedback MOSFET M3X is connected to the drain terminal of the fourth MOSFET M4 and thus also to the drain terminal of the second MOSFET M2.
The drain and source terminals of the second feedback MOSFET M4X are connected, respectively, to the drain terminal of the fourth MOSFET M4 and to the second node N2. The gate terminal of the second feedback MOSFET M4X is connected to the drain terminal of the third MOSFET M3, and thus also to the drain terminals of the first MOSFET M1 and of the first feedback MOSFET M3X. The gate terminal of the first feedback MOSFET M3X is thus connected also to the drain terminal of the second feedback MOSFET M4X.
The first and second feedback MOSFETs M3X, M4X implement a sort of positive feedback. In fact, assuming that we still haveIB1=(IB0/2)+ΔIB2=(IB0/2)−Δ,with Δ positive, the increase in the voltage present on the drain terminal of the third MOSFET M3, simultaneous to the decrease in the voltage present on the drain terminal of the fourth MOSFET M4, causes increase of the voltage present on the gate terminal of the second feedback MOSFET M4X, this increase tending to cause in turn an acceleration of the reduction in the voltage present on the drain terminal of the fourth MOSFET M4. In an altogether specular or mirrored way, the reduction in the voltage present on the drain terminal of the fourth MOSFET M4, simultaneous with the increase in the voltage present on the drain terminal of the third MOSFET M3, tends to cause an acceleration of the increase of the voltage present on the drain terminal of the third MOSFET M3.
In greater detail, the impedance seen from the drain terminal of the first MOSFET M1 towards the second node N2 is(gm−gmx)−1where gmx is the transconductance of the first and second feedback MOSFETs M3X, M4X.
In even greater detail, the behavior of the comparator circuit 10 depends upon the transconductances gm, gmx, and thus upon the W/L ratios for the channels of the third and fourth MOSFETs M3, M4 and of the first and second feedback MOSFETs M3X, M4X. In particular, if W/L(M3,M4) is the ratio between the width and the length of the channel of one of the third and fourth MOSFETs M3, M4 and if W/L(M3X,M4X) is the ratio between the width and the length of the channel of one of the first and second feedback MOSFETs M3X, M4X, we have the following conditions:                if W/L(M3,M4)>W/L(M3X,M4X), the negative-feedback mechanism guaranteed by the third and fourth MOSFETs M3, M4, which are diode-connected, prevails over the positive-feedback mechanism represented by the first and second feedback MOSFETs M3X, M4X, which are cross-coupled; consequently, the comparator circuit 10 operates in a way similar to what has been described with reference to the comparator circuit 1, but with faster decision times and higher gain;        if W/L(M3,M4)<W/L(M3X,M4X), the positive-feedback mechanism prevails slightly over the negative-feedback mechanism; consequently, the comparator circuit 10 has a response with hysteresis and may not be used as continuous-time comparator; and        if W/L(M3,M4)<<W/L(M3X,M4X), the positive-feedback mechanism prevails over the negative-feedback mechanism to the point where, once the comparator circuit 10 has carried out switching, it is no longer able to reset; consequently, also in this case the comparator circuit 10 may not be used as continuous-time comparator.        
For practical purposes, the comparator circuit 10 enables continuous-time monitoring of the input signal and thus enables detection of the instant at which the input signal crosses the voltage level of the reference signal. However, the comparator circuit 10, and more in general continuous-time comparators, has a decision time, and thus a speed, that is less than clock-triggered comparators. Further, the resolution of the comparator circuit 10 is not particularly high.